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; iop 480 aa de sign no te re v . 1 . 3 m a r c h 20 02 desig n no te d o cume nta t io n a . a f fected silicon r e v i sion t h is d o c um en t d e t a ils de sign no te s f o r th e f o llo w i n g silico n : p r oduc t part nu m b er de s c r i ption st at u s io p 48 0 aa io p48 0 - a a60 p i 6 0 m h z lo ca l b u s 208- p i n pq f p pr od uc t in pr od uc tio n o c tob e r 19 99 io p 48 0 aa io p48 0 - a a66 p i 6 6 m h z lo ca l b u s 208- p i n pq f p pr od uc t in pr od uc tio n o c tob e r 19 99 io p 48 0 aa io p48 0 - a a60 b i 6 0 m h z lo ca l b u s 225- p i n pbg a pr oduc t in pr od uc tio n o c tob e r 19 99 io p 48 0 aa io p48 0 - a a66 b i 6 6 m h z lo ca l b u s 225- p i n pbg a pr oduc t in pr od uc tio n o c tob e r 19 99 b. documentati on status t h e f o llo w i n g d o c um en ta tion is t h e b a s e line fu n c tion a l de scrip tio n of th e silicon . errata are de f i ned as b ehav iors in th e a ffect e d silicon t hat do not match beh av i o r s detai l ed i n t h i s doc um ent ati o n . document re v i s i on de s c r i ption p ublic a t ion d a te io p 48 0 da ta book 2.0 rele as ed d a ta bo ok j u l y 200 0 io p 48 0 aa er r a ta see www. pl x t ec h.c o m f o r l a te st re v i sio n io p 48 0 er r a ta doc u m entatio n c. desi gn note summar y # de s c r i ption 1 end- of - t r ansf e r ( e o t ) dur i ng ch ai nin g d m a en d l i nk mod e w i th w r ite- back 2 dma cha nne l 2 wit h e nd- o f - t r ansf e r ( e ot x # ) as s e r t ed c o inc i de nt with ad s# 3 z e r o w a it state sra m w r it es 4 ex ter n a l l o c a l m a s t er w r ite to io p 480 in ter n a l c onf ig ur atio n r e g i s t er s w i t h w a i t # bei ng us e d to i n s e rt w a it s t at es 5 mod i f y in g i n ter n al c o nf igur a t ion r egis t er s that af f e c t on- goi ng tr a n s f er s 6 o per ati on of io p 48 0 b u f f e r s in 3.3 v o lt si gn al ing en v i r onm ent 7 lcsx # c h i p s e l e c t out put del a y e d when io p 480 is i n iti a ti ng ac c e s s to sr am 8 com pac tpci hot s w ap i n s e r t ion b i t stat us 9 dmp a f # ( d ir ec t m a s t er pr ogr am m able alm o s t f u l l ) n egat ion tim i ng 10 mes s agi ng u n it dat a c o r r u p t ion if q ueu e pr ef etc h ( i nbo und f r e e l i s t f i f o pr ef etc h an d/or o u tbou nd pos t l i s t f i f o p r ef etc h ) is enab le d 11 loc al bus t i m eout w i t h sd ram 12 w a i t # inpu t s i g nal w h e n u s ing t he m e m o r y c ontr o ll er confidential doc u m ent num ber : dn- io p 48 0 re v aa- sil- 1 . 3 - 1-
13 al e o u tp ut t i m i ng 14 pci d e la y e d r ead mo de b i t ( p cict l[25]) 15 po w e r ma nag em ent inter f ac e spec if ic atio n ver s io n s u ppor t d. design notes 1. end-of-tr a nsfer (eot) duri ng chaini ng d m a end li n k m ode w i th w r it e-back d esign is sue : w hen w r ite back cy cles are enabl ed (c0mo d e[16]=1 and/or c1m o de[16]=1 ) dur i n g d m a tr ans f e r s w i th chai ni ng ena bl ed ( c 0m od e[9]= 1 and/ or c1 mode [9 ]=1 ) , t h e i o p 4 8 0 w ill w r ite b a ck t o th e dma d e scrip t o r a v a lu e of z e ro i n the by te co unt f i el d. h o w e v e r , i f t he eo t x # end li nk mo de i s al so ena bl ed ( c 0m od e[20]= 1 and /o r c 1 m o d e [20]= 1 ) and an e o t x # occur s r i g h t as th e l a st data i n t he d m a l i n k h a s be en tr ans fer r ed, t h e subs eq uent w r i t e ba ck o f z e r o hap pens tw ice. both write backs w ill w r ite to t he sa m e ad dress w i th the s a me v a l ue 0 ( z er o) . recommendation : t h er e sh oul d be no no ti ceabl e i m p a ct ex cept for w a v e f o r m s l o oki n g a bi t odd . 2. d m a channel 2 w i th end- of-transfer (eotx#) asse rted coincident w i th a d s# d esign is sue : if an en d o f t r ans fer ( e ot x # ) i s asser t ed w hen t he i o p 4 8 0 i s asse r t i n g ad s# during a dma cha nnel 2 trans fer, tw o (2 ) w o rds w ill be trans f e rred rather t h a n one ( 1 ) w o r d b e f or e th e d m a ter m i nat es. d m a 0 a nd 1, on t he oth e r han d, tr ans f e r onl y one ( 1 ) w o r d i f a n eo t x # i s ass e r t ed on t he s a me cl oc k cy cl e as ad s#. confidential doc u m ent num ber : dn- io p 48 0 re v aa- sil- 1 . 3 - 2-
3. z e ro w a it sta t e s r a m w r ites d esign is sue : t h e me mor y contr o l l e r con f i g ur ati o n r e g i ster s al l o w setti ng s for z e r o w a i t state sr am w r i t es. h o w e v e r , the iop 480 do es n o t sup por t z e r o w a i t stat e w r i t es to asy n chr onous sr am o n th e l o cal bus. zer o w a i t stat e r e a d s f r o m ex ter nal asy n chr onous sr am a r e una ffect ed as t hey d o no t r e q u i r e th e tog g l i n g o f th e m w e # si g nal . recommendations : 1. u s e 1 w a i t stat e w r i t es w hen accessi ng ex ter nal asy n chr o n ous sr a m ( w dd=1 ) . 2. u s e sd r a m i n ste ad o f sr am f o r fast access es to me m o r y . 3. u s e sbsr am . 4. externa l local ma ster w r ite to iop 4 80 in te rn al confi gur ati on r e gister s w i th w a i t # bei ng used to i n s e r t w a it states d esign is sue : t h e w a i t # i npu t ca n b e use d by an ex ter nal l o cal b u s m a ster to i n s e r t w a i t states w hen accessi ng the iop 480 i n ter nal c o n f i g ur ati o n r e g i ster s o r w hen accessi ng the pc i bus dur i n g direct master a ccesses. d u r i ng a con f i g ur ati o n w r i t e, w a i t # must be asser t ed ( b y the ex ter n al l o cal m a st er) a m i nimum o f t w o (2) clocks be f o re r eady # is asserte d by the i o p 480, for the iop 48 0 t o se n s e th e w a i t # i npu t. t h e ear l i e st r e ad y # w i l l be asser t e d is sev en (7) clocks a f t e r the ass e rtion o f ads # . t her e f ore, in ord e r t o ens ure t hat w a i t # i s r e cog n i z ed b y the iop 480 , w a i t # shoul d be asser t ed no l a ter th an f i v e (5) clocks a fter t h e a ssertion o f ads#. an y assertion o f w a i t # m o re tha n f i v e (5) clocks a fter t h e assertion o f ads# m a y be ig nored by the io p 48 0. if th e io p 4 80 does no t sens e w a i t # it w ill si m p ly assert ready # for one clock ( and t h i n k t he cy cl e ha s end ed) i n st ea d o f w a i t i n g unti l w a i t # has b e en neg a te d. t h i s pr obl e m appl i e s o n l y w hen an ex ter nal l o cal mas t er i s w r i t i n g to the i o p 480 i n ter nal c o n f i g ur ati o n r e g i ster s. confidential doc u m ent num ber : dn- io p 48 0 re v aa- sil- 1 . 3 - 3-
recommendation : d u r i ng a local m a s t er w r i t e to th e io p 4 80 i n t e r nal co n f i g ur ati on r e g i ster s, asser t w a i t # no later t h a n f i v e (5) clocks a fter t he a ssertion o f ads # , w h ich w ill ensure that the iop 48 0 recog n iz es w a i t # at le ast t w o (2) clocks be f o re it asserts r ead y # . 5. m odi f y i ng i n ter n al confi gur ati on regi ste r s that affe ct o n - goi ng tr ansfe r s d esign is sue : iop 4 80 i n ter n al r e g i ster setti ng s ( w hi ch mo di f y ong oi ng cy cl es) sho u l d n o t b e modi f i ed unti l t he c h i p i s no l o ng er doi ng suc h cy cl es. for ex ampl e, t u r n i n g o f f bur s t en abl e i n t he mi ddl e o f a bur st i s pr ohi bi ted. 6. operat ion of iop 480 buffers in 3 . 3 volt s i gnaling env i r onment d esign is sue : t h e io p 4 80 has uni v e r s al bu ffer s th at w e r e d e si g ned to op er at e i n e i ther a 5 vol t or 3.3 vol t si g nal i n g env i r onment. t h e io p 48 0 h a s a 3.3 vol t c o r e an d t he i/o b u f f e r s ar e 5 volt t o ler ant. t h e pc i v 2 .2 speci f i c a t i on sp eci f i e s cl a m p di odes to bot h g r ound a nd vc c w hen oper ati n g i n 3. 3 vol t si g nal i n g env i r onment . i n th e 5 vol t si g nal i n g e n v i r onment, the hi g h cl am p di o de i s opti o nal . the pur pos e o f th e cl a m p di od es i s t o ens u r e the relia bility and sig n a l integ r ity of th e receiv ing dev ices w hen there are ex cessi v e v o l t ag e tr an si ents o n t he bus a nd t o i m pr ov e pc i bus si g nal i n t e g r i t y . t h e io p 4 80 bu ffer s h a v e a cl am p di ode to g r ound, bu t n o si ng l e di ode to vc c ( t he iop 48 0 act ual l y has sev e r a l di o des i n s e r i es) . base d o n r e l i abi l i t y and sign a l in te grity e v a l u a t io n s , t h e iop 4 8 0 w ill o p e r a t e p r o p e r ly in b o t h 5 v o lt a n d 3.3 v o l t si g nal i n g env i r onm ents i n l i k el y ci r c ui t con f i g ur ati o ns ev en t h oug h i t has mul t i p l e hi g h cl a m p di o des i n s e r i es. s o m e o f the r e s u l t s o f ci r c ui t si mul a ti ons ar e descr i bed bel ow . if the iop 480 i s to be used i n a co n f i g ur ati o n th at ex ceeds th e condi ti o n s o f th ese si m u l a ti ons , pl e a se c ont ac t plx . t h e io p 4 80 bu ffer s ar e no t susc epti b l e to da mag e f r o m i n put si g nal v o l t ag e tr ansi ents cal l e d ou t by the s peci f i c a t i on ( u p t o 7. 1 vol t s) . in fact, th e iop 48 0 w i l l oper ate r e l i a bl y w i t hstan d i n g v o l t ag e spi k es as hi g h as 1 1 v o l t s. confidential doc u m ent num ber : dn- io p 48 0 re v aa- sil- 1 . 3 - 4-
t h e r e sp onse o f the io p 48 0 pc i i npu t bu ffer s w e r e si mul a te d u nde r v a r i ous ex tr eme co n f i g ur ati ons . for ex ampl e, w i th a 1 2 ? pc i tr ace l e ng th, 90 ohms bus i m pe danc e, 0 d e g r ees c e l s i u s, 3.6 vol t s and bei ng dr i v en by a str ong outp u t bu ffer ( t he iop 480 out put bu ffer h a s 35 o h m out put i m p e d a nce) , th e iop 4 80 c o r r e ctl y i n ter p r e ted th e di st or ted di g i tal w a v e f o r m i n t o t he c o r r e ct i deal di g i tal w a v e f o r m . gr aphs o f t h i s an d o t h e r w a v e f o r m s ar e av ai l abl e f r o m y our plx ar ea sal e s m anag er s or faes . t h er e f or e , i f t he i o p 4 80 i s p a r t o f a 3.3 vol t ci r c ui t that c o n nects to other pc i dev ices, it w ill properly interpret dist ort ed sig n a ls. i f t here are non-io p 48 0 d e v ice s o n t h e p c i bus, th e y w ill a l so b e a b l e to i n te rp ret d i sto r t e d sign a l s pr oper l y i f t hey cont ai n hi g h cl am p di o des. 7. lcsx# chi p se l e c t output del a y e d w h en i o p 480 is init iating access t o sra m d esign is sue : if d r a m r e f r esh cy cl es ar e e nabl ed ( d e f a u l t ) , ong o i n g r e f r esh cy cl es w i ll pr eemp t lc sx # asser t i on. w h e n th e io p 48 0 i s a b o u t to i n i t i a t e a cy cl e on th e l o cal bus ( i n one o f t he lc sx # r e g i ons) , d r a m r e f r esh cy cl es may come i n a nd j u mp ahe ad o f t he lc sx # as ser t i on. i n t h i s case , a d s#, a l e, and th e l o c a l ad dr ess w i ll still be g enerate d , but lcsx # w i l l not b e g enerat ed until t he re f r e s h cy cle is co m p l e ted . an y d a t a be in g tra n s f e rred w ill re m a in o n th e b u s d u r in g th is time (w ai ti ng f o r r ead y # ) , so as a r e sul t ther e i s no i m pact to the da ta tr ans f e r . h o w e v e r , the mul t i p l e x ed a ddr ess on the lad bus may hav e ch ang e d to dat a by the ti me lc sx # i s f i nal l y g ener ated ( w hen th e r e f r es h cy cl e has end e d ) . recommendation : 1. latch th e d e - m ul ti pl ex ed a ddr ess on the m a bus i n st ead o f the lad bus. 2. al w a y s l a tch ad dr esse s w i th ad s# or a l e r e g a r d l e ss o f lc sx #. 3. t u r n o ff r e f r esh cy cl es w hen not usi n g d r a m . 8. compactpci hot s w ap i n se r t i on bi t status d esign is sue : t h e io p 4 80 ho t sw ap inser t io n bit ( h scsr [7]) de faults to z e r o ( 0 ) a f ter r e s e t. t h i s c an be c onsi d er e d a v i ol ati on o f pic m g 2.1 r 1 .0 c o m pactpc i h o t sw ap sp e c i f ica t ion . t h is c o nd itio n w ill ca u s e a p r o b le m i f t h e b o a r d sw itch is clo s e d confidential doc u m ent num ber : dn- io p 48 0 re v aa- sil- 1 . 3 - 5-
pr i o r to r e se t ( r s t #) b e i n g neg ate d , or i f th e sy stem has be en pow er ed up w i th the i o p 480 i n ser t e d . recommendation : 1. t h e b oar d sw i t ch ne ed s to b e cl os ed a f ter pc i r e set ( r s t #) i s neg at ed. 2. so f t w a r e sho u l d al w a ys choos e a n ex tr acti on pr oced ur e for th e sa fe ter m i n ati on o f the c o m pactpc i h o t sw ap a d a p ter f r o m t he backpl a n e . 9. d m p a f# (direct master programma ble a l most full) negati on ti mi ng specif i c a t i on c l arif i c at ion: t h e mul t i p l e x ed pi n lc s0#/d m paf # i s co n f i g ur ed for d m paf# outp u t functi o nal i t y i f the loc a l bus c o n t r o l r e g i ster i s set t o 1 ( l oc c t l[0] = 1 ) . t h e de f a ul t pi n con f i g ur a t i o n i s lc s0 # functi o nal i t y . d m paf# pi n out put as ser t i on r e l i e s on t he pr og r a mm abl e v a l ue i n d m pbam [12: 8] t o d e ter m i ne w hen t o si g nal th at t he d i r e ct m a ster w r i t e fifo i s al mos t f u ll. af te r dmp a f # a s se rt io n , th e i o p 4 8 0 nega t e s t h e dmp a f # p i n u p o n th e la st w o r d of t he tr ans fer en ter i ng into t he da ta o u t holding reg i ster . the dm paf# si g nal i ndi cates the d i r ect m a ster w r i t e fif o status, no t th e co mpl e t i on o f th e tr ans f e r st atus . 10. m essag i ng uni t d a ta corr upti on i f q u eue pr efe t ch ( i nbound fr ee list f i fo pr e f etch and/ or outb ound post li st f i fo prefetch) is enabled d esign is sue : w hen th e me s s a g in g un it is e n a b l e d (mq cr[ 0 ] =1 ), t h e i n b o u n d fre e l i s t f i fo hol ds t he mess ag e f r a m e addr esses ( m f a) o f av ai l abl e messag e fr ames ( a v a i l abl e to a n ex ter n al pc i ag en t) i n sh ar ed local me mor y . t h e o u tbo und pos t li st fifo h o l d s t he m f a o f al l cur r entl y post e d m e ssag e s ( des ti ne d to a n ex ter nal pc i ag en t) th at ar e i n sh ar ed local me mor y . t o r educ e r e a d l a t ency , q ueue pr e f etchi n g ca n be en abl e d ( q sr [2 ] = 1 and /or qsr [ 3]= 1 ) . h o w e v e r , i f q u eue pr e f etchi n g i s ena bl ed, the m e ssag i n g u n i t data can r e t u r n i n cor r e ct da ta d ue t o i n t e r nal upd at i n g of th e p o i n ter s . confidential doc u m ent num ber : dn- io p 48 0 re v aa- sil- 1 . 3 - 6-
recommendation : d i s abl e q ueu e pr e f etc h i n g for th e m e ssag i ng u n i t by di sabl i n g th e qsr r e g i ster bi ts ( q sr [2]= 0 an d q s r [ 3]= 0 , the de faul t v a l ues) . 11. local bus timeout w i th sdra m d esign is sue : w hen a local bus tr ans a ction att e mpts t o acc e ss an inv a lid address , the l o cal bus ti meo u t feat ur e i n the i o p 48 0 ca n b e us ed to av oi d hang i n g th e l o c a l bus. h o w e v e r , w hen a l o cal bus ti me out occur s w hen t her e i s sd r a m i n t he sy stem, th is w ill ca u s e th e s dra m sta t e ma ch ine ba c k to t h e p o w e r on st a t e , re qu irin g a re -in i t i a l i z a t io n t o s t a r t u p a g a i n . w hen th e s dra m is in t h e p o w e r on state , a r e f r esh r e q uest c ann ot be i ssu ed, so th at w hen the iop 480 r e f r esh tim e r ex pires, t he re f r e s h req uest w ill be log ged b u t not c o mplet ed. t h is w ill pr ecl ude any ot her tr a n sacti o n on to the l o cal bus, and th e l o cal bus w i l l hang . recommendations : 1. if usi n g th e io p 4 80 w i th sd r a m , d o n o t c o u n t o n th e l o c a l bus ti m eout feat ur e to be abl e to r e cov e r f r o m i n v a l i d ad dr ess access es. 2. u s e so f t w a r e w o r k ar ounds t o r e cov e r f r o m thi s condi ti on. 12. w a i t # i nput si gnal w h en usi ng the m e mor y co ntr o l l e r d esign is sue : t h e w a i t # i npu t si g n a l i s not r e c o g n i z ed by the io p48 0 me mor y contr o l l e r dur i n g ex ter nal l o cal b u s m a ster tr a n sacti ons . ther e f or e, w hen w a i t # i s asser t ed by the ex ter nal l o cal b u s mast er dur i n g such a tr ansac ti on, the me m o r y controller w ill continue to carry out t he tra n sac t ion, ig noring th e w a i t # inp u t si g nal . recommendation : t h e f o l l o w i ng sol u ti on shoul d be i m pl em ent e d w i th ex ter nal g l ue l o g i c: a) m oni tor th e l o cal bus a ddr ess a nd w a i t #. b) if w a i t # i s asser t e d to the iop 480 w h i l e the iop 4 80 me mor y contr o l l e r i s per f o r m i n g a tr ans ac ti on i n i t i a ted by an ex te r nal l o cal b u s mast er , asser t blas t# ( t o t he iop 48 0) and asser t a b o ff# ( t o th e ex ter nal mas t e r ) . confidential doc u m ent num ber : dn- io p 48 0 re v aa- sil- 1 . 3 - 7-
13. a l e output ti mi ng data book change : fi g u r e 19- 1 i n t he iop 480 d a ta book r 1 .0 an d r 2 .0 s how s a t i mi ng d i a g r am f o r the a l e si g nal that i s i n cor r e ct. a l e ti mi ng i s dep end ent on th e l o c a l c l o ck per i od, w h i c h w a s not show n i n the ex i s ti ng di ag r a m. 1. t h e f o l l o w i ng di ag r a m cor r e ctl y show s the al e ti mi ng sp eci f i c ati o ns: 1. 5 v 1. 5v addr e s s bus 4. 3 / 9 . 3 3.7 / 8. 3 4. 0 / 10. 0 loc a l cloc k ale lc hi g h + 0 . 6/ 1. 0 lc hi g h 3. 8 / 8. 6 14. pci de l a y e d read m ode bi t (pci ctl[25]) data book change : t h e n a m e for the pc i bus c o n t r o l r e g i ster bi t 25 ( p c i c t l[ 25]) i s c h ang ed f r o m ? p c i d e l a y ed r ead m ode? t o ? p c i r 2 . 1 fe atu r es ena b l e ? . i o p 480 d a ta b ook secti on 4.5 , a nd t he p c ic t l [ 25] r e g i ster bi t descr i p ti on , ar e r e v i sed: confidential doc u m ent num ber : dn- io p 48 0 re v aa- sil- 1 . 3 - 8-
reg i st er 17- 6 3 . ( p cict l ; pci: 98h , l o c: 98h ) p c i b u s co n t ro l bit d escr iption r ead wr ite value after r eset 25 pci r2.1 f eat u r es en ab le. w hen s e t to 1, t he io p 4 8 0 per f o r m s all pci rea d a nd w r ite tr ans ac tions in c o m p li anc e with pci r 2 .1. se tti ng t h is bit ena bles d e l a y e d r eads , 2 15 pci c l oc k tim eout on re tr i e s , 16- a nd 8- c l oc k pci lat enc y r u les , a nd e n a b les t he opt i on to s e lec t pci rea d no w r ite mode ( r etr i es f o r w r i t es ) ( b it [2 5]) an d/or pci r e a d w i t h w r ite f l us h mo de ( b it [ 26]) . ref e r to s e c t io n 4. 5 f o r add iti ona l i n f o r m ation. val ue of 0 c aus es t r d y # t o r e m a in de- as s e r t ed on r e ads unti l r ead dat a is a v a i lab l e. if read d a ta is no t a v a ila bl e bef or e the pci t a r get retr y de la y c l oc k s c ounter ( l brd0 [31: 28]) ex pir e s , a pci r e tr y is is s u e d . p, l p, l , e 1 4.5 pci r2.1 f eat u r es en a b le t he io p 48 0 c an be pr ogr a m m ed thr ough the pci r 2 .1 f eatur es ena b l e b i t ( p cic t l[25]) to perf o rm all pci rea d / w ri te trans ac t i ons in c o m p lia n c e to p c i r2. 1 (and pc i r2. 2 ). t he f o llo wing io p 480 beh av ior oc c u r s w h en pcict l [25] = 1. 4.5.1 dir ect slav e d e la ye d read m o d e pci bus s i n g l e c y c l e a l i gne d or un al ig ned 32- b i t d i r e c t sl av e re ad tr a n s a c t io ns a l wa y s r e s u lt i n a 1- l w or d s i n g le c y c l e tr ans f e r on th e l o c a l b u s , w i t h c o r r e s pon din g l o c a l addr es s a nd b y t e ena b l e s ( l be[ 3:0] #) as s e r t ed to r e f l ec t the pci b y te en abl es ( c /be[ 3:0] #) , u n les s th e p c i rea d a h e ad m ode b i t is enab le d ( p ci ct l[22] = 1) ( r ef er to sec t i on 4 . 6) . t h is c aus es t he io p 48 0 to retr y a ll pci bus re ad r e ques ts t hat f o l l o w , unti l t he or ig ina l p c i addr e s s and b y te e nab les ( c / b e [ 3:0] #) ar e m a tc hed. 4.5.2 2 15 p c i cloc k t i me out if a pci m a s t er d oes no t c o m p lete its or i g i nal l y r e q ues t ed d i r e c t s l a v e d e l a y e d r ead tr ans f e r , the io p 48 0 f l us he s the d i r e c t s l a v e r ead f i f o af ter 2 15 pci c l oc k s and w i ll gr ant a n ac c e s s to a ne w d i r e c t s l a v e r ead ac c e s s . t he io p 48 0 retr ies a ll oth e r dir e c t sla v e re ad ac c e s s e s tha t oc c u r bef or e the 2 15 pci c l oc k ti m eout. 4.5.3 pc i r 2 .1 16- an d 8- clo ck ru le t he io p 48 0 gu ar ant ees th at if the f i r s t d i r e c t s l a v e w r ite d a ta c a nno t be ac c epte d b y the io p 48 0 a nd/or the f i r s t dir e c t sla v e rea d d a ta c a nnot be r e t u r n e d b y th e io p 48 0 with in 16 pci c l oc k s f r o m t he b egi nn ing of the d i r e c t sla v e c y c l e ( f ra me# as s e r t ed) , th e io p 48 0 is s ues a retr y ( s t o p# as s e r t e d ) to t he pci b u s . dur i ng s u c c e s s f ul dir e c t sla v e re ad a nd/ or dir e c t s l a v e w r ite ac c e s s e s , the s ubs eque nt d a ta af ter the f i r s t ac c e s s is ac c epted f o r w r it es or r e tur n e d f o r r eads in 8 pci c l oc k s ( t rdy # as s e r t ed) . o t her w i s e , the io p 480 is s ues a pci d i s c onn ec t ( s t o p# as s e r t e d ) to t he pci ma s t er . in ad dit i o n , s e tt ing the pc i r 2 .1 f e a t ur es e nab le bit ( p cict l[25] = 1) a l l o w s op tio nal enab li ng of the f o ll o w ing p c i r 2 .1 f unc ti ons : retr y pci w r ites dur i ng pe ndi ng r eads ( p cict l[24]) f l us h pen d in g re ads o n p c i w r ites ( p cict l[23]) confidential doc u m ent num ber : dn- io p 48 0 re v aa- sil- 1 . 3 - 9-
15. po w e r m a nageme nt i n te r f ace specifi cati on v e r s i on su ppor t d esign is sue : t h e io p 4 80 d a ta b o o k i ndi cat e s co mpl i anc e w i th the pc i pow e r m anag e m en t inter f ac e s peci f i c ati on r e v i si on 1.1, h o w e v e r t he pm c r e g i ster descr i p ti on i s compl i a nt w i th r e v i si on 1.0. t h e iop 48 0 ca n supp or t ei t her r e v i si on. t h e onl y di ffer enc es b e tw een t h ese r e v i si ons, w i th r e spect t o io p 4 80 s upp o r t, ar e t he ver s i on bi ts [2 :0] v a l u e ( p r o g r amm abl e by ee pr om or by l o cal bus pr ocessor ) , and the descr i p ti ons fo r bi ts [8: 6 , 4 ] for w h i c h the v a l ues ar e r e a d - onl y and r e tur n a v a l ue o f 0 r e g a r d l e ss o f r e v i si on. t h e v e r s i on bi ts v a l ue ( 0 0 1b or 010 b ) , w h i c h has n o e ffect on iop 4 80 o per ati on, i s use d b y sof t w a r e to det er mi n e pm c r e g i ster f o r m at . recommendation : pm c r e g i ster descr i p ti ons for r e v i si ons 1.0 a nd 1 . 1 ar e l i s ted bel ow . i f r e v i si on 1.1 r a t her t h a n r e v i si on 1.0 i s to be s upp or ted , pr og r a m t he pm c r e g i ster ( v i a eepr om or l o c a l bus pr ocessor ) w i th the ve r s i on v a l ue ( 010 b) to o v erw r i t e the pm c r e g i ster de f aul t v a l ue, by chang i n g the 32- bi t v a l ue at e epr o m o f f s et e8 h or local bus o f f s e t 3 4 0 h , f r o m 0 0 0 154 01h to 000 254 01h . regist er 10- 2 7 . ( p m c ; pci : 42h, lo c: 342) pow e r m a nagement cap a bilit ie s (pci pow e r m g mt. r1 .0 ) bit d escr iption r ead wr ite value aft e r r eset 2: 0 ve r s ion . the val u e 001 i ndi c a t e s c o m p l i a n c e w i t h p c i p o w e r m g m t . r 1 .0 . ye s l, e 001 3 pc i c l oc k r e q u ir e d f o r p m e# si gna l. v a l ue o f 1 i ndi c a t e s a f unc t i on rel i e s on p c i cl ock pre s e n c e f o r p m e # operat i on. the i o p 480 doe s no t requi re t h e p c i cl oc k f o r p m e # , s o t h i s bi t s houl d s e t t o 0 . ye s l, e 0 4 a u xi l i ar y p o w e r s ource . b e c ause t he i o p 480 does not s upport p m e # w h i l e i n a d3c o l d st at e, t h i s bi t i s al w a ys s e t t o 0 . ye s no 0 5 devi ce-s p eci fi c i n i t i a l i z ati o n (d s i ). v a l ue o f 1i ndi c a t e s t he i o p 480 requi res s p e c i a l i n i t i a l i zat i on f o l l o w i ng a t r an s i t i on t o a d0 uni ni t i al i z ed s t a t e be f o re a gen eri c c l ass devi c e dri v er i s abl e to u s e i t . ye s l, e 0 8: 6 reserved. ye s no 000 9 d 1_support . v a l u e of 1 i ndi c a t e s t he i o p 480 s upport s t h e d1 pow e r s t at e . ye s no 0 10 d 2_support . v a l u e of 1 i ndi c a t e s t he i o p 480 s upport s t h e d2 pow e r s t at e . ye s no 0 15: 11 p m e supp ort . i ndi c a t e s pow er s t at es i n w h i c h t he i o p 480 m a y ass e rt p m e # . v a l ues: x x x x 1 = p m e # c an be a s s e rt ed f r om d0 xxx1 x = p m e # c a n b e a s s e r t e d fr o m d1 x x 1 x x = p m e # c an be a s s e rt ed f r om d2 x 1 x x x = p m e # c an be a s s e rt ed f r om d3hot x x x x x = p m e # c annot be a s s e r t ed f r o m d3 c o l d ye s [ 14: 11] : l, e [ 15] : no 00000 confidential doc u m ent num ber : dn- io p 48 0 re v aa- sil- 1 . 3 - 10-
confidential document number: dn-iop 480 rev aa-sil-1.3 - 11- register 10-27. (pmc; pci:42h, loc:342) power management capabilities (pci power mgmt. r1.1) bit description read write value after reset 2:0 version. the default value 001 indicates compliance with pci power mgmt. r1.1. to instead indicate pmc register format compliance with revision 1.1, this value should be set to 010. yes local 001 3 pci clock required for pme# signal. value of 1 indicates a function relies on pci clock presence for pme# operation. the iop 480 does not require the pci clock for pme#, so this bit should set to 0. yes local 0 4 reserved. yes no 0 5 device-specific initialization (dsi). value of 1 indicates the iop 480 requires special initialization following a transition to a d0 un-initialized state before a generic class device driver is able to use it. yes l, e 0 8:6 aux_current. supported by way of the pmdata register per pci power mgmt. r1.1. yes no 000 9 d1_support. value of 1 indicates the iop 480 supports the d1 power state. yes l, e 0 10 d2_support. value of 1 indicates the iop 480 supports the d1 power state. yes l, e 0 15:11 pme support. indicates power states in which the iop 480 may assert pme#. values: xxxx1 = pme# can be asserted from d0 xxx1x = pme# can be asserted from d1 xx1xx = pme# can be asserted from d2 x1xxx = pme# can be asserted from d3hot xxxxx = pme# cannot be asserted from d3cold yes [14:11]: l, e [15]: no 00000 copyright 2002 by plx technology, inc. all rights reserved. plx is a trademark of plx technology, inc. which may be registered in some jurisdictions. all other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. information supplied by plx is believed to be accurate and reliable, but plx technology, inc. assumes no responsibility for any errors that may appear in this material. plx technology reserves the right, without notice, to make changes in product design or specification.

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